1. Field of the Invention
The present invention relates generally to the synchronous transmission and synchronization of digitally encoded data between a central processor and a plurality of terminals or other computer and associated peripheral equipment for utilizing or operating with such transmitted data. More specifically, the invention relates to a system for extending the allowable transmission line length between a computer and its associated terminal devices beyond the length possible with systems of the prior art.
When digitally encoded data, in whatever format, such as phase encoded, sometimes referred to as Manchester encoding, NRZ, or other known code is transmitted over a transmission line, the phase error between the data transitions and the system clock increases with increasing transmission line distance until the resultant bit-shift results in loss of synchronization between the clock and data and errors in the transmitted data. The terms phase shift, bit shift and peak shift are used interchangeably herein to described the well known phenomena of the shifting of data transitions during transmission. The present invention relates to a technique for retiming the data at some point or points along the transmission line with a newly generated retiming clock which is phase adjustable with the incoming data, and for retransmitting the retimed data along the transmission line, thereby extending the distance possible between a central processor and its terminals by substantially reducing the phase shift errors which would otherwise occur in transmission.
An exemplary application for such a retiming system is a central processor from which data is coupled to a plurality of electronic cash registers, as for example, in a department store.
2. Description of the Prior Art
Many communications systems are known in the prior art for transmitting digital data serially, in parallel, synchronously and asynchronously between a computer and its associated peripheral equipment. While such data may usually be synchronously transmitted from the computer to the peripheral equipment, data from the peripherals, in multi-byte format, is generally asynchronously transmitted to the computer, since the time or origin of such data is usually random and intermittent. The present invention relates to an improved synchronous transmission system for retiming and retransmitting synchronous data.
A typical communication system for the prior art illustrative of synchronous data communication between a central computer and its data terminals is disclosed by U.S. Pat. No. 3,676,846. A plurality of prior art repeaters in a trasmission line for transmitting pulsed information is disclosed by U.S. Pat. No. 3,072,744. Another repearter technique for a bidirectional communication system is disclosed by U.S. Pat. No 3,040,130. A serial loop data transmission system is disclosed by U.S. Pat. No. 3,633,166. A multi-clock timing control for a multiprocessor system is disclosed by U.S. Pat. No. 3,715,729. None of the above-identified prior art patents utilize the digital phase locked loop resynchronization and transmission line extension techniques of the present invention wherein correction pulses are either added or substracted from the retiming clock in accordance with a continuous digital comparison of the retiming clock and the data transitions, with such correction dependent upon the detected phase error exceeding a predetermined digital value.